This invention relates to a semiconductor random access memory (RAM) element capable of providing a large scale integration and a method of manufacturing the same.
FIG. 1 is a sectional view showing a prior art standard one transistor dynamic RAM element or cell which comprises one memory capacitor and a switching MOS transistor.
The dynamic RAM cell is formed on a semiconductor substrate 1 including a thick field oxide film 2 and a channel stopping layer 3. The memory capacitor for storing information comprises a thin insulating film 4 and a metal plate 5. The switching MOS transistor also comprises a gate insulating film 6, a gate electrode 7 connected to an address line, a diffused layer 8 connected to one end of the memory capacitor, and a diffused layer 10 connected to a bit line 9.
When an address line is selected, the switching MOS transistor is turned ON, permitting electric charge to flow either into or out of the memory capacitor when read or write selection is actuated.
Recently, the memory cell size per bit is decreasing with years, and 256K bit dynamic RAM devices are ready for being placed on the market.
However, the reduction of the memory cell size has weakened dynamic RAM devices in the immunity to .alpha. rays or noise.
Under these conditions, with the prior art memory cell structure, it has been difficult to boost the packing density of IC memory devices without degrading the electrical characteristics.